A construction of a conventional CCD imager will be described with reference to FIGS. 5 to 7. FIG. 5 is a cross-sectional view showing a construction of a conventional CCD imager and FIG. 7 is a plan view showing the device of FIG. 5.
In FIGS. 5 and 6, the conventional CCD imager is constituted by a semiconductor substrate 1, a silicon dioxide film 2 produced on the semiconductor substrate 1, and polycrystalline silicon gates 3 produced on the silicon dioxide film 2. In the figure drawn in the semiconductor substrate 1, reference numeral 4 designates a potential barrier against electron flow and reference numeral 5 designates signal charges. In FIG. 7, reference numeral 3 designates a polycrystalline silicon gate and reference numeral 6 designates a photodiode.
As is understood from FIGS. 5 to 7, in order to transfer charges stored at the photodiode 6, the number of CCD transfer gates required for one photodiode is "4". That is, when constructing an imager using a two-phase or four-phase driving system CCD, four gates are required to carry out the transfer of charges and if the number of gates is less than that, mixing of charges occurs. Also, in a three-phase driving system CCD, three gates are required to carry out the transfer of charges. The two-phase driving system is most generally used because only two kinds of input clocks are required.
In an imager, it is desirable that the density of pixels increase and it is preferred that the number of CCD transfer gates be reduced compared to the increase in the number of pixels. With these goals in mind, a new CCD driving system is proposed in an article by A. J. P. Theuwissen et al, "The Accordion Imager: an Ultra High Density Frame Transfer CCD", IEDM 84, Lec.No.2.6, Prescripts pp. 40 to 43.
FIGS. 8(a)-8(n) show a structure and a manner driving of the accordion system CCD device described in that article. In FIGS. 8(b)-8(h), potentials at times t.sub.1 to t.sub.7, respectively, are shown. At time t.sub.1, charges exist at all potential wells. That is, two gate electrodes are provided corresponding to signal charges stored at one photodiode and this structure is very advantageous for integration of photodiodes. When the transfer is started after time t.sub.2, charges successively move from the output side.
FIG. 9 shows clock inputs for realizing the operation shown in FIGS. 8(b)-8(n). In FIG. 9, high and low voltages are alternatingly applied to respective electrodes at time t.sub.1 and in correspondence with the advance of time as t.sub.2, t.sub.3, . . . , the clocks applied to respective electrodes are successively inverted from the output side. Shift registers connected to respective electrodes include a circuit as shown in FIG. 10, that is, a CMOS inverter 14 including P and N channel transistors 15 and 16, respectively, and an N channel transistor 17 connected to the input terminal of the inverter 14.
FIG. 11(a) shows a circuit diagram in which the circuit of FIG. 10 is connected as is actually used. In FIG. 11(b) while in the stationary state where input clocks .phi..sub.IN do not change, the voltages on the electrodes after the input clock .phi..sub.IN are regularly and alternatingly high(H) or low(L), when the input clock .phi..sub.IN changes from H to L or from L to H, the change is transferred as a voltage change of the electrode after the clock .phi..sub.1 in synchronization with the two driving clocks .phi..sub.A, .phi..sub.B. It is possible to realize the potential distribution shown in FIGS. 8(b)-(n) by using these clock inputs. In FIG. 11(b), the L or H clock whose voltage is changed is surrounded by a circle (.largecircle.) in order to clarify the transfer of the voltage change.
The conventional CCD imager is constructed as described above, and clocks .phi..sub.A, .phi..sub.B for driving the shift registers, the switching transistors and inverters corresponding to respective electrode gates are required, thereby complicating the circuit construction.